The present invention relates to an analyzing device for saving memory failures which is used with equipment for testing what is called a redundant-structured semiconductor memory having spare (or redundancy) lines which are used as substitutes for failing address lines.
As shown in FIG. 1, the redundant-structured memory has, on the outside of its memory area 11, column spare address lines 12 extending in parallel to its column address lines (and each having formed thereon memory cells of the corresponding column) and row spare lines 13 extending in parallel to row address lines (and each having formed thereon memory cells of the corresponding row), and when a fail is found in a function test of the memory, the failing row or column address line, i.e. the row or column address line including the failing cell, is electrically replaced with the spare line so that the memory can be used as a nondefective.
In the case where a failure is found in the memory area of the redundant-structured memory, the address of the failing cell is located, a check is made whether all failures are recoverable or not with spare lines, and if they are recoverable, it is analyzed which of the row and column spare lines should be substituted for the failing cells so as to use the memory as a nondefective. This analysis will hereinafter be referred to as an analysis for failure saving.
Data necessary for the failure saving analysis are the total number of failing cells (or fails) in the memory area (or an analysis block) 11 (which number will hereinafter be referred to as the total fail count TFC), the number of failing cells (or fails) on each row address line (which number will hereinafter be referred to as the row address fail count RFC) and the number of failing cells (or fails) on each column address line (which number will hereinafter be referred to as the column address fail count CFC). That is, the number of failing cells on the row address line RA.sub.i and the number of failing cells on the column address line CA.sub.j in the memory area 11 are counted as indicated by RFC(i) and CFC(j) in FIG. 2.
A description will be given first of a conventional method of such an analysis for failure saving. As shown in FIG. 3, during testing of a memory under test 15 an address RACA and data D available from a pattern generator 14 are provided to the memory 15 to write therein the data D at a memory cell specified by the address RACA, the stored content of the memory cell is read out, the read-out signal S is compared by a logic comparator 15 with an expected value E from the pattern generator 14, and when they do not match, a failure analysis memory 17 is accessed using the address RACA and a "1" is written thereinto.
After completion of a series of tests the failure analysis memory 17 is read out to obtain the data TFC, RFC and CFC necessary for the failure saving analysis. In this instance, as depicted in FIG. 4A, cells on row address lines RA.sub.0, RA.sub.1, . . . of the failure analysis memory 17 are read out to count the numbers of "1s" on the respective row address lines and hence obtain count values RFC(0), RFC(1), . . . Then, as shown in Fig. 4B, the numbers of "1s" on respective column address lines CA.sub.0, CA.sub.1, . . . of the failure analysis memory 17 are similarly counted to obtain count values CFC(0), CFC(1), . . . Thereafter, the row address fail counts RFC(0), RFC(1), . . . or column address fail counts CFC(0), CFC(1), . . . are added up to obtain the total fail count TFC.
Based on the total number of failing cells or the value of the total fail count TFC thus obtained, a check is made for the presence or absence of failing cells in the analysis block (i.e. the memory area) and for the possibility of saving the failing cells. That is to say, the maximum number of failing cells which can be saved by use of all the spare lines is compared with the total fail count TFC, making a check to see if the latter exceeds the former. Letting the numbers of row addresses RA and column addresses CA of the analysis block be represented by I and J, respectively, and the numbers of row spare address lines and column spare address lines by M and N, respectively, the maximum number of failing cells which can be saved is expressed by J.M+I.N-M.N.
Next, the detection of failing address lines and the assignment of spare lines (for saving them) are made, based on the data RFC and CFC, and then the row address fail counts RFC, the column address fail counts CFC and the total fail count TFC are updated accordingly. The number of failing cells RFC(i)=A (a variable) on the row address line RAi is compared with the number of usable column spare lines N=B (a variable), and when a line failure condition A &gt;B holds, the row address line RAi is detected as a failing address line. That is, when A&gt;B, the number of column spare lines is insufficient to save all failing cells on the row address line RAi. Therefore, it is necessary to use one of the row spare lines for saving the failing cells on the row address line RAi. Thus, the row address line for which the line failure condition A&gt;B holds is regarded as a failing address line. Similarly, the number of failing cells CFC(j) on each column address line CAj.tbd.A is compared with the number of row spare lines M.tbd.B, and when A&gt;B, the column address line CAj is judged as a failing address line to be substituted with a column spare line.
When the failing address lines are thus detected and decided to be substituted with the spare lines or saved, the data RFC, CFC and TFC are each updated to a value having subtracted the number of failing cells on each saved failing address line from its initial fail count. At the same time, the numbers of spare lines M and N that can be used for saving are also updated accordingly and the line failure condition A&gt;B is checked again for each line. These operations are repeated.
After the removal of all failing address lines the remaining failing cells are saved by a method which starts the save with the address line having the largest number of failing cells, or a round robin algorithm. Then it is determined whether or not the memory under test can ultimately be used as a non-defective product, and if so, the address value of each address line containing the failing cells to be replaced with the spare line is obtained as a solution of the failure saving analysis.
As mentioned above, the prior art involves the counting of the number of failing cells for each row address line and for each column address line for obtaining the fail counts RFC and CFC, and hence calls for accessing twice the failure analysis memory 17 over the entire area of one analysis block--this consumes an appreciable amount of time. In addition, since each row (or column) address line is read out within a specified column (or row) address range and the number of "1s" in the range is counted, processes such as the readout of the address line, the specification of the address range to be read out next and starting of the operation are performed for each address line; so that much time is needed for obtaining the row address fail counts RFC and the column address fail counts CFC. Also in the case of simultaneously testing a plurality of memories, the processing for obtaining the counts RFC and CFC from the failure analysis memory 17 is performed for each memory under test, and consequently, much time is consumed for obtaining the values RFC, CFC and TFC for all of the memories under test.
Conventionally, the detection of a failing address line is made by comparing, for instance, the number of column spare lines M (=B) with the number of failing cells RFC(i) (=A) on each row address line RAi, and if the line failure condition (A&gt;B) holds, then the element number i of the row address fail count RFC(i) is stored as a failing address in a memory and the count value of failing row address lines is incremented by one. Similar processing is performed for the number of failing cells CFC(j) (=A) on each column address line CAj and the failing address on the column address line is also stored in the memory. These processes by software are relatively time-consuming. Also in the case of simultaneously testing two or more memories, the above-mentioned detection of failing address lines and their storage into the memory are effected for each memory under test, so that the processing time is long as a whole.
Upon determination of the saving of failing address lines, defective cells thereon are removed and the data RFC, CFC and TFC are updated. In the prior art, for example, when an address 5 of the row address is decided to be saved as a failing address line, the row address fail count RFC (5) is subtracted from the total fail count TFC to update the latter and the former is reduced to zero. Next, the row address is fixed to the address 5, the column address is incremented sequentially from an address 0, the failure analysis memory 17 is accessed for each column address, and upon each readout of a "1" therefrom, the column address fail count CFC corresponding to that column address is decremented by one. This operation is repeated until the maximum value of the column address is reached, whereby the column address fail count CFC is updated. Thus, the illustrated prior art example takes much time for the updating of the column address fail count CFC. The same is true of the updating of the row address fail count RFC in the case of saving a column address line.